DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 385

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

9.8
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width. In phase counting mode, the phase difference and
overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at
least 2.5 states. Figure 9.44 shows the input clock conditions in phase counting mode.
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
Where f : Counter frequency
Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
TCLKA
(TCLKC)
TCLKB
(TCLKD)
φ : Operating frequency
N : TGR set value
f = ————
Notes: Phase difference and overlap
Usage Notes
(N + 1)
Pulse width
φ
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 1.5 states or more
: 2.5 states or more
Phase
differ-
ence
Pulse width
Rev.7.00 Dec. 24, 2008 Page 331 of 698
Pulse width
Pulse width
REJ09B0074-0700