DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 45

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Figure 17.13 Program/Program-Verify Flowchart....................................................................... 580
Figure 17.14 Erase/Erase-Verify Flowchart ................................................................................ 582
Figure 17.15 Memory Map in Programmer Mode....................................................................... 585
Figure 17.16 Power-On/Off Timing (Boot Mode)....................................................................... 589
Figure 17.17 Power-On/Off Timing (User Program Mode) ........................................................ 590
Figure 17.18 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)............................. 591
Section 18 Masked ROM
Figure 18.1 Block Diagram of On-Chip Masked ROM (64 kbytes).......................................... 593
Section 19 Clock Pulse Generator
Figure 19.1 Block Diagram of Clock Pulse Generator .............................................................. 595
Figure 19.2 Connection of Crystal Resonator (Example).......................................................... 600
Figure 19.3 Crystal Resonator Equivalent Circuit ..................................................................... 600
Figure 19.4 External Clock Input (Examples) ........................................................................... 601
Figure 19.5 External Clock Input Timing.................................................................................. 602
Figure 19.6 Example Connection of 32.768-kHz Quartz Oscillator.......................................... 603
Figure 19.7 Equivalence Circuit for 32.768-kHz Oscillator ...................................................... 603
Figure 19.8 Pin Handling when Subclock Not Required........................................................... 603
Figure 19.9 Example of PLL Circuit ......................................................................................... 604
Figure 19.10 Note on Board Design of Oscillator Circuit ........................................................... 605
Figure 19.11 Example of External Clock Switching Circuit ....................................................... 606
Figure 19.12 Example of External Clock Switchover Timing..................................................... 606
Section 20 Power-Down Modes
Figure 20.1 Mode Transition Diagram ...................................................................................... 609
Figure 20.2 Example of Flash Memory Module Stop Mode Usage .......................................... 616
Figure 20.3 Medium-Speed Mode Transition and Clearance Timing ....................................... 618
Figure 20.4 Software Standby Mode Application Example ...................................................... 621
Figure 20.5 Hardware Standby Mode Timing (Example) ......................................................... 622
Figure 20.6 Timing of Transition to Hardware Standby Mode ................................................. 622
Figure 20.7 Timing of Recovery from Hardware Standby Mode.............................................. 623
Section 2 Electrical Characteristics
Figure 22.1 Power Supply Voltage and Operating Ranges........................................................ 658
Figure 22.2 Output Load Circuit................................................................................................ 663
Figure 22.3 System Clock Timing............................................................................................. 665
Figure 22.4 Oscillation Stabilization Timing............................................................................. 665
Figure 22.5 Reset Input Timing................................................................................................. 667
Figure 22.6 Interrupt Input Timing............................................................................................ 667
Rev.7.00 Dec. 24, 2008 Page xlv of liv
REJ09B0074-0700