DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 635

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

17.8.2
When erasing flash memory, the erase/erase-verify flowchart shown in Figure 17.14 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E1 bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
register 1, 2 (EBR1, EBR2). To erase multiple blocks, each block must be erased in turn.
An overflow cycle of approximately (y+z+α+β) ms is allowed.
is B'0. Verify data can be read in longwords from the address to which a dummy write was
performed.
before. The maximum number of repetitions of the erase/erase-verify sequence is N.
Erase/Erase-Verify
Rev.7.00 Dec. 24, 2008 Page 581 of 698
REJ09B0074-0700