DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 127

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
Note: * Supported only by the H8S/2218 Group.
Bit
7
6
5
4
3
2
1
0
Bit Name
INTM1
INTM0
NMIEG
MRESE
RAME
Initial Value R/W
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The write value should always be 0.
Reserved
This bit is always read as 0 and cannot be modified.
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
1: An interrupt is requested at the rising edge of NMI
Manual Reset Select
Enables or disables the MRES pin* input.
0: Manual reset is disabled
1: Manual reset is enabled
The MRES input pin* can be used.
Reserved
This bit is always read as 0 and cannot be modified.
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
input
input
Rev.7.00 Dec. 24, 2008 Page 73 of 698
REJ09B0074-0700

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