DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 463

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

and clear TDRE flag in SSR to 0
Clear DR to 0 and set DDR to 1
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Figure 12.10 Sample Serial Data Transmission Flowchart
Break output?
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Rev.7.00 Dec. 24, 2008 Page 409 of 698
SCI initialization:
The TxD pin is automatically designated
as the transmit data output pin.
After the TE bit is set to 1, a frame of 1s
is output, and transmission is enabled.
SCI status check and transmit data write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Serial transmission continuation
procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that writing
is possible, then write data to TDR, and
then clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC is activated
by a transmit data empty interrupt (TXI)
request, and data is written to TDR.
Break output at the end of serial
transmission:
To output a break in serial transmission,
set DDR for the port corresponding to the
TxD pin to 1, clear DR to 0, then clear the
TE bit in SCR to 0.
REJ09B0074-0700