DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 619

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

17.5.5
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed. For
details, refer to section 17.7, Flash Memory Emulation in RAM.
Bit
7 to 4 —
3
2
1
0
Bit Name Initial Value
RAMS
RAM2
RAM1
RAM0
RAM Emulation Register (RAMER)
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits always read as 0. The write value should
always be 0.
RAM Select
Specifies selection or non-selection of flash memory
emulation in RAM. When RAMS = 1, the flash memory
is overlapped with part of RAM, and all flash memory
block are program/erase-protected.
Flash Memory Area Selection
When the RAMS bit is set to 1, selects one of the
following flash memory areas to overlap the RAM area.
The areas correspond with 1-kbyte erase blocks.
000: H'000000 to H'0003FF (EB0)
001: H'000400 to H'0007FF (EB1)
010: H'000800 to H'000BFF (EB2)
011: H'000C00 to H'000FFF (EB3)
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev.7.00 Dec. 24, 2008 Page 565 of 698
REJ09B0074-0700