DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 237

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

7.4.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to
0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCR. On completion of the
specified number of transfers, MAR and ETCRL are automatically restored to their original
settings and operation continues. One address is specified by MAR, and the other by IOAR. The
transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register
functions in repeat mode.
Table 7.5
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
Register
23
23
H'FF
15
7
7
Repeat Mode
ETCRH
ETCRL
MAR
Register Functions in Repeat Mode
IOAR
0
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Holds number of transfers
Transfer counter
Function
DTDIR = 1
Destination
address
register
Source
address
register
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Fixed
Number of transfers Decremented every
Rev.7.00 Dec. 24, 2008 Page 183 of 698
Operation
Incremented/decrem
ented every transfer.
Initial setting is
restored when value
reaches H'0000
Fixed
transfer. Loaded
with ETCRH value
when count reaches
H'00
REJ09B0074-0700