DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 138

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 4.3
Legend:
×: Don't care
A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a
manual reset.
When the MRES pin* is used, MRES pin* input must be enabled by setting the MRESE bit to 1 in
SYSCR.
Note:* Supported only by the H8S/2218 Group.
4.3.2
When the RES or MRES* pin goes low, this LSI enters the reset. To ensure that this LSI is reset,
hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the
RES or MRES* pin low for at least 20 states.
When the RES or MRES* pin goes high after being held low for the necessary time, this LSI starts
reset exception handling as follows.
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized,
2. The reset exception handling vector address is read and transferred to the PC, and program
Note: * Supported only by the H8S/2218 Group.
Figures 4.1 and 4.2 show examples of the reset sequence.
Rev.7.00 Dec. 24, 2008 Page 84 of 698
REJ09B0074-0700
Type
Power-on reset
Manual reset
the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
Reset Exception Handling
Reset Types
MRES
×
Low
Reset Transition Condition
RES
Low
High
CPU
Initialized
Initialized
On-Chip Peripheral Modules
Initialized
Initialized, except for bus
controller and I/O ports
Internal State