DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 426

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Rev.7.00 Dec. 24, 2008 Page 372 of 698
REJ09B0074-0700
Bit
5
4
3
2
1
0
Bit Name Initial Value
PE
O/E
BCP1
BCP0
CKS1
CKS0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Parity Enable
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception. Set this bit to 1 in smart card
interface mode.
Parity Mode (valid only when the PE bit is 1)
0: Selects even parity
1: Selects odd parity
For details on the usage of this bit in smart card interface
mode, see section 12.7.2, Data Format (Except for Block
Transfer Mode).
Basic Clock Pulse 1 and 0
These bits select the number of basic clock cycles in a 1-
bit data transfer time in smart card interface mode.
00: 32 clock cycles (S = 32)
01: 64 clock cycles (S = 64)
10: 372 clock cycles (S = 372)
11: 256 clock cycles (S = 256)
For details, see section 12.7.5, Receive Data Sampling
Timing and Reception Margin. S is described in section
12.3.11, Bit Rate Register (BRR).
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 12.3.11, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 12.3.11, Bit Rate Register (BRR)).