DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 518
DF2211NP24V
Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.DF2211NP24V.pdf
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5. If a pin with pull-up function is SAMPLEed with pull-up function enabled, the corresponding
6. If a pin with open-drain function is SAMPLEed while its open-drain function is enabled and
7. If EXTEST, CLAMP, or HIGHZ state is entered, this LSI enters guarded mode such as
8. The EMLE pin must be cleared to 0. When the pin is set to 1, this chip functions as High-
Rev.7.00 Dec. 24, 2008 Page 464 of 698
REJ09B0074-0700
EMLE Pin
0
1
IN register is set to 1. In this case, the corresponding Control register must be cleared to 0.
while the corresponding OUT register is set to 1, the corresponding Control register is cleared
to 0 (the pin status is Hi-Z). If the pin is SAMPLEed while the corresponding OUT register is
cleared to 0, the corresponding Control register is set to 1 (the pin status is 0).
hardware standby mode (RES = STBY = 0). Before entering normal operating mode from
EXTEST, CLAMP, or HIGHZ state, specify RES, STBY, FWE, and MD2 to MD0 pin to the
designated mode.
performance user debugging interface (H-UDI).
Chip State
Normal operation, boundary scan function
High-performance user debugging interface (H-UDI)
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