DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 240

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

7.4.5
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single
transfer request, and this is executed the number of times specified in ETCRA. The transfer source
is specified by MARA, and the transfer destination by MARB. Table 7.6 summarizes register
functions in normal mode.
Table 7.6
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU. The maximum
number of transfers, when H'0000 is set in ETCRA, is 65,536.
Rev.7.00 Dec. 24, 2008 Page 186 of 698
REJ09B0074-0700
Register
23
23
15
Normal Mode
ETCRA
MARA
MARB
Register Functions in Normal Mode
0
0
0
Function
Source address
register
Destination address
register
Transfer counter
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Number of transfers Decremented every
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000