DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 363

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

9.5.3
Buffer operation, provided for channel 0, enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register. Table 9.17 shows the register combinations used in buffer
operation.
Table 9.17 Register Combinations in Buffer Operation
• When TGR is an output compare register
• When TGR is an input capture register
Channel
0
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. This operation is illustrated in figure 9.16.
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register. This operation is
illustrated in figure 9.17.
Buffer Operation
Buffer register
Buffer register
Input capture
signal
Figure 9.16 Compare Match Buffer Operation
Figure 9.17 Input Capture Buffer Operation
Timer General Register
TGRA_0
TGRB_0
Compare match signal
Timer general
register
Timer general
register
Rev.7.00 Dec. 24, 2008 Page 309 of 698
Comparator
Buffer Register
TGRC_0
TGRD_0
TCNT
TCNT
REJ09B0074-0700