DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 460

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
Note: * Figure 12.6 shows an example when the ABCS bit of SEMRA_0 is cleared to 0. When
12.4.3
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used. When an external clock is selected, the basic
clock of average transfer rate can be selected according to the ACS2 to ACS0 bit setting of
SEMR_0.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin by
setting CKE1 = 0 and CKE0 = 1. The frequency of the clock output in this case is equal to the bit
rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as
shown in figure 12.7.
Rev.7.00 Dec. 24, 2008 Page 406 of 698
REJ09B0074-0700
SCK
TxD
Figure 12.7 Relationship between Output Clock and Transfer Data Phase
Clock
ABCS is set to 1, the clock frequency of basic clock is 8 times the bit rate and the
receive data is sampled at the rising edge of the 4th pulse of the basic clock.
0
D0
D1
D2
(Asynchronous Mode)
D3
D4
1 frame
D5
D6
D7
0/1
1
1

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