DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 437

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Note:
12.3.8
SCMR is a register that selects the transfer format. In this LSI, Smart Card interface mode cannot
be specified.
Bit
1
0
Bit
7 to 4 —
3
2
1
0
Bit Name Initial Value R/W
MPB
MPBT
Bit Name Initial Value
DIR
INV
—
SMIF
1. The write value should always be 0 to clear the flag.
2. To clear the flag by the CPU on the HD6432210S, reread the flag after writing 0 to it.
Smart Card Mode Register (SCMR)
0
0
All 1
0
0
1
0
R
R/W
R/W
—
R/W
R/W
—
R/W
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Description
Reserved
These bits are always read as 1.
Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data format
is 8 bits.
Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. To invert
the parity bit, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
1: TDR contents are inverted before being transmitted.
This bit is always read as 1.
Smart Card Interface Mode Select
When this bit is set to 1, smart card interface mode is
selected.
0: Normal asynchronous or clocked synchronous mode
1: Smart card interface mode
Description
Reserved
data is stored as it is in RDR
Receive data is stored in inverted form in RDR
Rev.7.00 Dec. 24, 2008 Page 383 of 698
REJ09B0074-0700