DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 342

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
Table 9.12 TIORL_0 (channel 0)
Legend:
×: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1and TGRC_0 is used as a buffer register, this
Rev.7.00 Dec. 24, 2008 Page 288 of 698
REJ09B0074-0700
Bit 3
IOC3
0
1
setting is invalid and input capture/output compare is not generated.
Bit 2
IOC2
0
1
0
1
Bit 1
IOC1
0
1
0
1
0
1
×
Bit 1
IOC0
0
1
0
1
0
1
0
1
0
1
×
×
TGRC_0
Function
Output
compare
register*
Input capture
register*
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
Initial output is 0 output
1 output at compare match
Initial output is 0 output
Toggle output at compare match
Output disabled
Initial output is 1 output
0 output at compare match
Initial output is 1 output
1 output at compare match
Initial output is 1 output
Toggle output at compare match
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
Capture input source is TIOCC0 pin
Input capture at both edges
Setting prohibited
Description

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