DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 253

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Full Address Mode (Burst Mode): Figure 7.17 shows a transfer example in which TEND* output
is enabled and word-size full address mode transfer (burst mode) is performed from external 16-
bit, 2-state access space to external 16-bit, 2-state access space.
In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the
transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle
is inserted after the DMA write cycle.
If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,
the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer
has already been activated inside the DMAC, the bus is released on completion of a one-byte or
one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer
cycle of the burst transfer has already been activated inside the DMAC, execution continues to the
end of the transfer even if the DTME bit is cleared.
Note: * This LSI does not support TEND output.
Address bus
TEND*
Note: * This LSI does not support TEND output.
HWR
LWR
Bus release
RD
Figure 7.17 Example of Full Address Mode (Burst Mode) Transfer
φ
DMA read
DMA write DMA read DMA write DMA read DMA write
Burst transfer
Rev.7.00 Dec. 24, 2008 Page 199 of 698
Last transfer cycle
DMA
dead
REJ09B0074-0700
Bus release