DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 474

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

12.6.2
Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the
SCI should be initialized as described in a sample flowchart in figure 12.18. When the operating
mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before
making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag
is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,
FER, and ORER flags, or the contents of RDR.
Rev.7.00 Dec. 24, 2008 Page 420 of 698
REJ09B0074-0700
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
SCI Initialization (Clocked Synchronous Mode)
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
to 0 or set to 1 simultaneously.
Set data transfer format in
1-bit interval elapsed?
Start initialization
Set value in BRR
SMR and SCMR
<Transfer start>
(TE, RE bits 0)
Figure 12.18 Sample SCI Initialization Flowchart
Yes
Wait
No
[2]
[3]
[4]
[1]
[1]
[2]
[3]
[4]
Set the clock selection in SCR. Be sure to
clear bits RIE, TIE, TEIE, and MPIE, TE and
RE, to 0.
Set the data transfer format in SMR and
SCMR.
Write a value corresponding to the bit rate to
BRR. Not necessary if an external clock is
used.
Wait at least one bit interval, then set the TE
bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE bits.
Setting the TE and RE bits enables the TxD
and RxD pins to be used.