H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 113

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.1
4.1.1
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
Overview
Exception Handling Types and Priority
Exception Type
Reset
Trace *
Interrupt
Trap instruction (TRAPA) *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows. The CPU
enters the power-on reset state when the NMI pin is high,
or the manual reset state when the NMI pin is low.
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued *
Started by execution of a trap instruction (TRAPA)
2
Rev. 3.00 Sep 15, 2006 page 79 of 988
Section 4 Exception Handling
REJ09B0330-0300