H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 312

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.12
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfers and internal
accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus master, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output is an external bus cycle. However, a low level is not output from the TEND pin if the bus
cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an
external write cycle is executed in parallel with this cycle.
Figure 7.33 shows an example of burst mode transfer from on-chip RAM to external memory
using the write data buffer function.
Rev. 3.00 Sep 15, 2006 page 278 of 988
REJ09B0330-0300
Figure 7.33 Example of Dual Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Write Data Buffer Function
HWR, LWR
TEND
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead