H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 958
H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
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Appendix B Internal I/O Register
TIOR1—Timer I/O Control Register 1
Rev. 3.00 Sep 15, 2006 page 924 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
:
:
:
TGR1B I/O Control
Legend: *: Don’t care
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
0
1
*
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR1B
is output
compare
register
TGR1B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCB 1 pin
Capture input
source is TGR0B
compare match/
input capture
IOB0
R/W
TGR1A I/O Control
Legend: *: Don’t care
4
0
0
1
0
1
0
1
IOA3
R/W
3
0
0
1
0
1
0
1
*
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR0B compare match/input
capture
0
1
0
1
0
1
0
1
0
1
*
*
IOA2
TGR1A
is output
compare
register
TGR1A
is input
capture
register
R/W
2
0
H'FFE2
IOA1
Output disabled
Initial output is
0 output
Output disabled
Initial output is
1 output
Capture input
source is
TIOCA 1 pin
Capture input
source is TGR0A
compare match/
input capture
R/W
1
0
IOA0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
channel 0/TGR0A compare match/
input capture
TPU1
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