H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 570

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Watchdog Timer (WDT)
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock ( ), for input to TCNT.
Note:
12.2.3
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For
Rev. 3.00 Sep 15, 2006 page 536 of 988
REJ09B0330-0300
Bit 2
CKS2
0
1
Bit
Initial value
R/W
Note: * Can only be written with 0 for flag clearing.
* The overflow period is the time from when TCNT starts counting up from H'00 until
Reset Control/Status Register (RSTCSR)
Bit 1
CKS1
0
1
0
1
details see section 12.2.4, Notes on Register Access.
overflow occurs.
:
:
:
R/(W) *
WOVF
Bit 0
CKS0
0
1
0
1
0
1
0
1
7
0
RSTE
R/W
Description
Clock
6
0
/2 (initial value)
/64
/128
/512
/2048
/8192
/32768
/131072
RSTS
R/W
5
0
Overflow Period (when
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
—
—
4
1
—
—
3
1
—
—
2
1
= 20 MHz) *
—
—
1
1
—
—
0
1