H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 455

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bits 7, 6, 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the
TCNT counter clearing source.
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
Channel
0, 3
Channel
1, 2, 4, 5
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
buffer register setting has priority, and compare match/input capture does not occur.
modified.
Bit 7
CCLR2
0
1
Bit 7
Reserved *
0
3
Bit 6
CCLR1
0
1
0
1
Bit 6
CCLR1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture *
TCNT cleared by TGRD compare match/input
capture *
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation *
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 421 of 988
2
2
1
1
1
REJ09B0330-0300
(Initial value)
(Initial value)