H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 257

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bits 13 and 12—Reserved: Can be read or written to.
Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when
DMA transfer is performed, of the internal interrupt source selected by the data transfer factor
setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor
setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal
interrupt source selected by the data transfer factor setting does not issue an interrupt request to the
CPU or DTC.
When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer
factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the
CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC
transfer.
When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues
an interrupt request to the CPU or DTC regardless of the DTA bit setting.
The state of the DTME bit does not affect the above operations.
Bit 11—Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor
setting.
Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA
transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor
setting.
Bit 11
DTA1
0
1
Bit 9
DTA0
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Rev. 3.00 Sep 15, 2006 page 223 of 988
Section 7 DMA Controller (DMAC)
REJ09B0330-0300
(Initial value)
(Initial value)