H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 319

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.7
DMAC Register Access during Operation
Except for forced termination, the operating (including transfer waiting state) channel setting
should not be changed. The operating channel setting should only be changed when transfer is
disabled.
Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address.
Figure 7.40 shows an example of the update timing for DMAC registers in dual address transfer
mode.
DMA Internal
address
DMA register
operation
DMA control
Consequently, MAR is updated in the bus cycle before DMAC transfer.
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Usage Notes
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Idle
[1]
Transfer
source
Read
Figure 7.40 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Rev. 3.00 Sep 15, 2006 page 285 of 988
Transfer
source
Read
Section 7 DMA Controller (DMAC)
[2]'
DMA read
DMA last transfer cycle
destination
Write
Transfer
DMA write
[3]
REJ09B0330-0300
Dead
DMA
dead
Idle