H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 217

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

(3) Relationship between Chip Select (CS
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
Figure 6.33 Relationship between Chip Select (CS
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
CS
CS) Signal and Read (RD
CS
Address bus
CS (area A)
CS (area B)
RD
Rev. 3.00 Sep 15, 2006 page 183 of 988
T
RD
RD) Signal
CS
CS) and Read (RD
RD
CS
1
Bus cycle A
(b) Idle cycle inserted
T
(Initial value ICIS1 = 1)
2
Section 6 Bus Controller
T
3
REJ09B0330-0300
T
RD
RD)
RD
I
Bus cycle B
T
1
T
2