H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 734

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 20 Power-Down Modes
20.8
Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle,
and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, clock output is disabled and input port mode is set.
Table 20.5 shows the state of the pin in each processing state.
Table 20.5
Rev. 3.00 Sep 15, 2006 page 700 of 988
REJ09B0330-0300
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
Clock Output Disabling Function
Pin State in Each Processing State
0
High impedance
High impedance
High impedance
High impedance
1
0
High impedance
Fixed high
output
output
1
1
High impedance
Fixed high
Fixed high
Fixed high

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