H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 410

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 I/O Ports
9.9.2
Table 9.15 shows the port B register configuration.
Table 9.15 Port B Registers
Note:
Port B Data Direction Register (PBDDR) [H8S/2351 Only]
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Rev. 3.00 Sep 15, 2006 page 376 of 988
REJ09B0330-0300
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Bit
Initial value
R/W
Modes 1, 4, and 5
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Modes 2 and 6
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while
clearing the bit to 0 makes the pin an input port.
Modes 3 and 7
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
* Lower 16 bits of the address.
Register Configuration [H8S/2351 Only]
:
:
:
PB7DDR
W
7
0
PB6DDR
W
6
0
PB5DDR
PBDDR
PBDR
PBPCR
Abbreviation
PORTB
W
5
0
PB4DDR
W
4
0
PB3DDR
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
PB2DDR
W
2
0
PB1DDR
W
1
0
H'FF6A
H'FF5A
Address *
H'FEBA
H'FF71
PB0DDR
W
0
0