H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 535

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation
takes precedence and the write to the buffer register is not performed.
Figure 10.55 shows the timing in this case.
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 10.55 Contention between Buffer Register Write and Input Capture
Buffer register write cycle
M
Buffer register
T1
address
N
T2
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 501 of 988
M
N
REJ09B0330-0300

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