H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 724

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 Power-Down Modes
20.2.3
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 15 to 0—Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See
table 20.3 for the method of selecting on-chip supporting modules.
20.3
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock ( /2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus
masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock ( ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
Rev. 3.00 Sep 15, 2006 page 690 of 988
REJ09B0330-0300
Bits 15 to 0
MSTP15 to MSTP0
0
1
Bit
Initial value
R/W
Module Stop Control Register (MSTPCR)
Medium-Speed Mode
:
:
:
R/W
15
0
R/W
14
0
Description
Module stop mode cleared
Module stop mode set
R/W
13
1
MSTPCRH
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
MSTPCRL
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1