H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 528

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 16-Bit Timer Pulse Unit (TPU)
10.7
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.48 shows the input clock
conditions in phase counting mode.
Caution on Period Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
Where f: Counter frequency
Rev. 3.00 Sep 15, 2006 page 494 of 988
REJ09B0330-0300
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Figure 10.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
N: TGR set value
f =
Usage Notes
: Operating frequency
Pulse width
(N + 1)
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 1.5 states or more
: 2.5 states or more
Phase
differ-
ence
Pulse width
Pulse width
Pulse width