H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 139

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Note:
5.4
5.4.1
Interrupt operations in the H8S/2350 Group differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated
by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.
Interrupt Source
ERI1 (receive error 1)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
TEI1 (transmission end 1)
Reserved
* Lower 16 bits of the start address.
Interrupt Operation
Interrupt Control Modes and Interrupt Operation
Origin of
Interrupt
Source
SCI
channel 1 85
Vector
Number
86
87
88
89
90
91
84
Normal
Mode
H'00AA
H'00AC
H'00AE
H'00B0
H'00B2
H'00B4
H'00B6
H'00A8
Vector Address *
Rev. 3.00 Sep 15, 2006 page 105 of 988
Advanced
Mode
H'0150
H'0154
H'0158
H'015C
H'0160
H'0164
H'0168
H'016C
Section 5 Interrupt Controller
IPR
IPRK6 to 4
IPRK2 to 0
REJ09B0330-0300
Priority
High
Low

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