H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 168

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write
data buffer function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 5—Reserved: Only 1 should be written to this bit.
Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface.
LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input
cannot be used when LCAS signal is used.
Rev. 3.00 Sep 15, 2006 page 134 of 988
REJ09B0330-0300
Bit 7
BRLE
0
1
Bit 6
BREQOE
0
1
Bit
Initial value
R/W
Bus Control Register L (BCRL)
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports.
External bus release is enabled.
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
:
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
R/W
—
5
1
LCASS
R/W
4
1
DDS
R/W
3
1
R/W
—
2
1
WDBE
R/W
1
0
(Initial value)
(Initial value)
WAITE
R/W
0
0