H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 314

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 7.13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not
be changed until the end of the transfer.
Figure 7.35 shows a transfer example in which transfer requests are issued simultaneously for
channels 0A, 0B, and 1.
7.5.14
There can be no break between a DMA cycle read and a DMA cycle write. This means that a
refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read
and external write in a DMA cycle.
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh
or external bus released state may be inserted after a write cycle. Since the DTC has a lower
priority than the DMAC, the DTC does not operate until the DMAC releases the bus.
Rev. 3.00 Sep 15, 2006 page 280 of 988
REJ09B0330-0300
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
RD
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 7.35 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Idle
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
DMA write
Read
DMA
read