H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 311

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

DREQ
DREQ
DREQ
DREQ Pin Low Level Activation Timing
Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7.32 shows an example of DREQ pin low level activated single address mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
Figure 7.32 Example of DREQ
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMAC cycle is started.
Acceptance is resumed after the single cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
[1]
Request
Bus release
Minimum of
2 cycles
DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ
DREQ
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
Rev. 3.00 Sep 15, 2006 page 277 of 988
[5]
Section 7 DMA Controller (DMAC)
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[7]
REJ09B0330-0300
release
Bus