H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 852

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Appendix B Internal I/O Register
TCR3—Timer Control Register 3
Rev. 3.00 Sep 15, 2006 page 818 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
:
:
:
CCLR2
R/W
7
0
Notes: 1.
Counter Clear
0
1
CCLR1
R/W
0
1
0
1
6
0
2.
0
1
0
1
0
1
0
1
Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture *
TCNT cleared by TGRD compare match/input capture *
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
CCLR0
R/W
5
0
CKEG1
Clock Edge
R/W
0
1
4
0
—
0
1
CKEG0
R/W
Count at rising edge
Count at falling edge
Count at both edges
3
0
Timer Prescaler
H'FE80
0
1
0
1
0
1
TPSC2
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on /1
Internal clock: counts on /4
Internal clock: counts on /16
Internal clock: counts on /64
External clock: counts on TCLKA pin input
Internal clock: counts on /1024
Internal clock: counts on /256
Internal clock: counts on /4096
TPSC1
R/W
1
0
2
2
TPSC0
1
1
R/W
0
0
TPU3