H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 498

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.4
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10.5 shows the register combinations used in buffer operation.
Table 10.5 Register Combinations in Buffer Operation
Rev. 3.00 Sep 15, 2006 page 464 of 988
REJ09B0330-0300
Channel
0
3
Buffer register
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.16.
Buffer Operation
Figure 10.16 Compare Match Buffer Operation
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Compare match signal
Timer general
register
Comparator
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
TCNT