H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 270

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.5.2
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.6 summarizes register functions in sequential mode.
Table 7.6
Legend:
MAR:
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Rev. 3.00 Sep 15, 2006 page 236 of 988
REJ09B0330-0300
Register
23
23
H'FF
Memory address register
Sequential Mode
15
15
Register Functions in Sequential Mode
MAR
ETCR
IOAR
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Transfer counter
Function
DTDIR = 1
Destination
address
register
Source
address
register
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers
Operation
Incremented/
decremented
every transfer
Fixed
Decremented
every transfer;
transfer ends
when count
reaches H'0000