H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 821

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

A.5
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Legend:
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
JMP@aa:24
Instruction
Bus States during Instruction Execution
Byte-size read
Word-size read
Byte-size write
Word-size write
Transfer of the bus is not performed immediately after this cycle
Address of 2nd word (3rd and 4th bytes)
Address of 3rd word (5th and 6th bytes)
Address of 4th word (7th and 8th bytes)
Address of 5th word (9th and 10th bytes)
Address of next instruction
Effective address
Vector address
R:W 2nd
1
Internal operation
1 state
2
R:W EA
3
4
Order of execution
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
Rev. 3.00 Sep 15, 2006 page 787 of 988
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Appendix A Instruction Set
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REJ09B0330-0300
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