H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 239

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2.4
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of
MAR every data transfer in sequential mode or repeat mode.
In idle mode, MAR is neither incremented nor decremented.
Bit 7
DTSZ
0
1
Bit 6
DTID
0
1
DMACR
Initial value
R/W
Bit
DMA Control Register (DMACR)
Description
Byte-size transfer
Word-size transfer
Description
MAR is incremented after a data transfer
MAR is decremented after a data transfer
:
:
:
:
When DTSZ = 0, MAR is incremented by 1 after a transfer
When DTSZ = 1, MAR is incremented by 2 after a transfer
When DTSZ = 0, MAR is decremented by 1 after a transfer
When DTSZ = 1, MAR is decremented by 2 after a transfer
DTSZ
R/W
7
0
DTID5
R/W
6
0
RPE
R/W
5
0
DTDIR
R/W
4
0
Rev. 3.00 Sep 15, 2006 page 205 of 988
DTF3
R/W
3
0
Section 7 DMA Controller (DMAC)
DTF2
R/W
2
0
DTF1
REJ09B0330-0300
R/W
1
0
(Initial value)
(Initial value)
DTF0
R/W
0
0