H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 459

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

10.2.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
TMDR register settings should be made only when TCNT operation is stopped.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Bit 5
BFB
0
1
Channel 0: TMDR0
Channel 3: TMDR3
Bit
Initial value
R/W
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit
Initial value
R/W
Timer Mode Register (TMDR)
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
:
:
:
:
:
:
—
—
—
—
7
1
7
1
—
—
—
—
6
1
6
1
BFB
R/W
—
—
5
0
5
0
BFA
R/W
—
—
4
0
4
0
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Sep 15, 2006 page 425 of 988
MD3
MD3
R/W
R/W
3
0
3
0
MD2
MD2
R/W
R/W
2
0
2
0
MD1
MD1
R/W
R/W
REJ09B0330-0300
1
0
1
0
(Initial value)
MD0
MD0
R/W
R/W
0
0
0
0