H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 249

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 7.4.
7.3.1
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 7.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2
IOAR is not used in full address transfer.
Bit
MAR
Initial value
R/W
Bit
MAR
Initial value
R/W
Register Descriptions (2) (Full Address Mode)
Memory Address Register (MAR)
I/O Address Register (IOAR)
:
:
:
:
:
:
:
:
R/W
31
15
—
—
0
*
R/W
30
14
—
—
0
*
R/W
29
13
—
—
0
*
R/W
28
12
—
—
0
*
R/W
27
11
—
—
0
*
R/W
26
10
—
—
0
*
R/W
25
—
—
0
9
*
R/W
24
—
—
0
8
*
R/W
R/W
Rev. 3.00 Sep 15, 2006 page 215 of 988
23
*
7
*
R/W
R/W
22
6
*
*
Section 7 DMA Controller (DMAC)
R/W
R/W
21
*
5
*
R/W
R/W
20
4
*
*
R/W
R/W
19
*
3
*
REJ09B0330-0300
R/W
R/W
18
2
*
*
*: Undefined
R/W
R/W
17
1
*
*
R/W
R/W
16
*
0
*