H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 441

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Bit
Initial value
R/W
0
Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351]
Pin PG
to 1, and as an input port when the bit is cleared to 0.
For pins PG
while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 [H8S/2351 only]
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351]
Pins PG
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG
setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit
to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus
Controller.
).
4
0
4
functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set
functions as the CAS output pin when DRAM interface is designated. Otherwise,
to PG
:
:
:
3
to PG
Undefined
1
function as bus control output pins (CS0 to CS3) when the corresponding
—
—
7
0
, setting the corresponding PGDDR bit to 1 makes the pin an output port,
Undefined
—
—
6
Undefined
—
—
5
PG4DR
R/W
4
0
Rev. 3.00 Sep 15, 2006 page 407 of 988
PG3DR
R/W
3
0
PG2DR
R/W
2
0
PG1DR
Section 9 I/O Ports
REJ09B0330-0300
R/W
1
0
PG0DR
4
R/W
to
0
0