H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 403

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: * Modes 2 3, 6, and 7 only applies to the H8S/2351.
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA
PA
PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port A Register (PORTA)
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset,
and in software standby mode.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PA
0
Mode 6 *
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing
the bit to 0 makes the pin an input port.
).
:
:
:
:
:
:
PA7DR
PA7
R/W
—*
R
7
7
0
PA6DR
PA6
R/W
—*
R
6
6
0
7
to PA
PA5DR
PA5
R/W
—*
R
7
5
0
5
0
) must always be performed on PADR.
to PA
0
PA4DR
.
PA4
R/W
—*
R
4
4
0
Rev. 3.00 Sep 15, 2006 page 369 of 988
PA3DR
PA3
R/W
—*
R
3
3
0
PA2DR
PA2
R/W
—*
R
2
2
0
Section 9 I/O Ports
PA1DR
REJ09B0330-0300
PA1
R/W
—*
R
1
1
0
PA0DR
7
PA0
R/W
—*
to
R
0
0
0