H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 297

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.5.9
Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
CPU cycle
DMAC cycle (1-word transfer)
CPU cycle
T
T
T
T
T
T
T
T
1
2
1
2
3
1
2
3
Source
Destination address
address
Address bus
RD
HWR
LWR
Figure 7.18 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev. 3.00 Sep 15, 2006 page 263 of 988
REJ09B0330-0300