H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 237

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2.2
IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source
address or destination address. The upper 8 bits of the transfer address are automatically set to
H'FF.
Whether IOAR functions as the source address register or as the destination address register can
be selected by means of the DTDIR bit in DMACR.
IOAR is invalid in single address mode.
IOAR is not incremented or decremented each time a transfer is executed, so that the address
specified by IOAR is fixed.
IOAR is not initialized by a reset or in standby mode.
7.2.3
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of
this register is different for sequential mode and idle mode on the one hand, and for repeat mode
on the other.
(1) Sequential Mode and Idle Mode
In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range
of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count
reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.
Bit
IOAR
Initial value
R/W
Transfer Counter
Bit
ETCR
Initial value
R/W
I/O Address Register (IOAR)
Execute Transfer Count Register (ETCR)
:
:
:
:
:
:
:
:
R/W
15
*
R/W
15
*
R/W
14
*
R/W
14
*
R/W
13
R/W
*
13
*
R/W
12
R/W
*
12
*
R/W
11
R/W
*
11
*
R/W
R/W
10
10
*
*
R/W
R/W
9
*
9
*
R/W
R/W
8
*
8
*
R/W
R/W
Rev. 3.00 Sep 15, 2006 page 203 of 988
7
7
*
*
R/W
R/W
6
*
6
Section 7 DMA Controller (DMAC)
*
R/W
R/W
5
*
5
*
R/W
R/W
4
*
4
*
R/W
R/W
3
*
3
*
REJ09B0330-0300
R/W
R/W
2
*
*: Undefined
2
*
*: Undefined
R/W
1
*
R/W
1
*
R/W
0
*
R/W
0
*