H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 717

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
19.4
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock ( ).
19.5
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32.
19.6
The bus master clock selection circuit selects the system clock ( ) or one of the medium-speed
clocks ( /2, /4, or /8, /16, and /32) to be supplied to the bus master, according to the settings
of the SCK2 to SCK0 bits in SCKCR.
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
Rev. 3.00 Sep 15, 2006 page 683 of 988
Section 19 Clock Pulse Generator
REJ09B0330-0300

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