H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 547

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Different Triggers for Pulse Output Groups
If pulse output groups 2 and 3 are triggered by different compare match events, the address of the
upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is
H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that
cannot be modified and are always read as 1.
If pulse output groups 0 and 1 are triggered by different compare match event, the address of the
upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F.
Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be
modified and are always read as 1.
Bit
Initial value
R/W
Bit
Initial value
R/W
Bit
Initial value
R/W
Bit
Initial value
R/W
Address H'FF4C
Address H'FF4E
Address H'FF4D
Address H'FF4F
:
:
:
:
:
:
:
:
:
:
:
:
NDR15
NDR7
R/W
R/W
7
1
7
0
7
1
7
0
NDR14
NDR6
R/W
R/W
6
0
6
1
6
1
6
0
NDR13
NDR5
R/W
R/W
5
0
5
1
5
0
5
1
Section 11 Programmable Pulse Generator (PPG)
NDR12
NDR4
R/W
R/W
4
0
4
1
4
1
4
0
Rev. 3.00 Sep 15, 2006 page 513 of 988
NDR11
NDR3
R/W
R/W
3
1
3
0
3
0
3
1
NDR10
NDR2
R/W
R/W
2
1
2
0
2
0
2
1
NDR1
NDR9
R/W
R/W
REJ09B0330-0300
1
1
1
0
1
1
1
0
NDR0
NDR8
R/W
R/W
0
1
0
0
0
0
0
1

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