H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 294

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
Activation by Internal Interrupt
An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU
and DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt, the DMAC accepts the request independently of the
interrupt controller. Consequently, interrupt controller priority settings are not accepted.
If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a
DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-
priority channel is activated first. Transfer requests for other channels are held pending in the
DMAC, and activation is carried out in order of priority.
When DTE = 0, such as after completion of a transfer, a request from the selected activation
source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt
request is sent to the CPU or DTC.
In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt
request flag is not cleared by the DMAC.
Activation by External Request
If an external request (DREQ pin) is specified as an activation source, the relevant port should be
set to input mode in advance.
Level sensing or edge sensing can be used for external requests.
External request operation in normal mode (short address mode or full address mode) is described
below.
When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low
transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is
input before transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is
held high. While the DREQ pin is held low, transfers continue in succession, with the bus being
released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a
transfer, the transfer is interrupted and the DMAC stands by for a transfer request.
Rev. 3.00 Sep 15, 2006 page 260 of 988
REJ09B0330-0300