H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 962

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Appendix B Internal I/O Register
TCR2—Timer Control Register 2
Bit
Initial value
Read/Write
Rev. 3.00 Sep 15, 2006 page 928 of 988
REJ09B0330-0300
:
:
:
7
0
Note: * Synchronous operating setting is performed by setting
Counter Clear
0
1
CCLR1
0
1
0
1
R/W
6
0
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
the SYNC bit TSYR to 1.
CCLR0
R/W
5
0
CKEG1
Note: This setting is ignored when channel 2
Clock Edge
R/W
4
0
0
1
is in phase counting mode.
0
1
CKEG0
R/W
Count at rising edge
Count at falling edge
Count at both edges
3
0
Note: This setting is ignored when channel 2 is in phase
Time Prescaler
H'FFF0
0
1
0
1
0
1
TPSC2
counting mode.
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on /1
Internal clock: counts on /4
Internal clock: counts on /16
Internal clock: counts on /64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on /1024
TPSC1
R/W
1
0
TPSC0
R/W
0
0
TPU2

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