H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 307

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Figure 7.28 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Address bus
DACK
TEND
RD
Figure 7.28 Example of Single Address Mode (Word Read) Transfer
release
Bus
DMA read
release
Bus
DMA read
Rev. 3.00 Sep 15, 2006 page 273 of 988
release
Bus
Section 7 DMA Controller (DMAC)
DMA read
Last transfer
cycle
REJ09B0330-0300
DMA
dead
release
Bus

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